1. Field of the Invention
The present invention relates to a driving method and a drive control circuit of a liquid crystal display device, and a liquid crystal display device including the same.
2. Description of the Related Art
In recent years, both the resolution and the display density of an active matrix type liquid crystal display device (LCD) have become remarkably high. In the case where the resolution is not very high, it is possible to sufficiently secure an on time (writing time) of a gate signal (gate pulse) applied to a gate electrode of a thin film transistor (TFT) formed as a liquid crystal drive switching element in each pixel. Thus, even if the voltage (gate-on voltage) of the gate pulse at the on time is not made high, a gradation voltage can be certainly written to a pixel electrode, and excellent display quality can be obtained. However, when the number of gate bus lines is increased in order to raise the resolution, in the case where a vertical scanning period is constant, the writing time becomes short, and insufficient writing of the gradation voltage can occur. As solving means of this problem, there is a method in which the gate-on voltage is made high to raise the mobility of the TFT.
However, there is a defect in the method of making the gate-on voltage high. The defect will be described with reference to FIGS. 16 and 17. FIG. 16 shows one gate bus line as a CR distributed constant circuit. As shown in FIG. 16, the gate bus line can be expressed as a circuit in which low-pass filters each composed of a resistance R and a capacitance C are continuously connected. In such a gate bus line, when the width of the gate bus line is made minute to increase the display density, the component of the resistance R is increased, and when the thickness of a gate insulating film is made thin, the component of the capacitance C is increased, and therefore, a gate delay occurs which can not be neglected.
FIG. 17 shows a state of the gate delay of the gate pulse applied to the gate bus line. When the resistance value, load capacitance and the like of the gate bus line itself are increased, as shown in FIG. 17, with respect to the gate pulse outputted to the gate bus line, a round waveform due to the delay hardly occurs in the vicinity of, for example, a pixel 1 at the side close to a gate driver, however, as the gate pulse goes away from the gate driver, for example, in the vicinity of a pixel n (n denotes the maximum number of pixels driven by one gate bus line), a round waveform as shown in the drawing occurs.
In an LCD which performs a color display with three primary colors of R (Red), G (Green) and B (Blue), the number of pixels driven by one gate bus line becomes the resolution in the direction of gate bus line extension ×3. For example, the number n of pixels driven by one gate bus line is 1920 (=640×3) in the case where the display system is VGA, n=3072 (=1024×3) in XGA, n=3840 (1280×3) in SXGA and n=4800 (1600×3) in UXGA. When the gate driver for driving gate bus lines outputs rectangular gate pulses at predetermined timings to the respective gate bus lines, the rectangular gate pulses are applied to the gate electrodes of the TFTs of the pixel 1, the pixel 2, the pixel 3 and the like which are close to the gate driver, however, the gate pulses with the round waveforms are applied to the gate electrodes of the TFTs of the pixel (n−1) and the pixel n which are remote from the gate driver. Since the writing condition of the gradation voltage to the pixel electrode is changed by the round waveform among pixels on the same gate bus line, a problem of uneven display and the like occurs. Since the round waveform due to the gate delay becomes remarkable as the gate-on voltage is made high, the display quality becomes apt to deteriorate.
FIGS. 18A to 18E show relation among a round waveform, a writing time and a writing amount. FIG. 18A shows a horizontal synchronizing signal a in the case where a horizontal scanning frequency is “A” kHz, FIG. 18B shows a horizontal synchronizing signal b in the case where a horizontal scanning frequency is “B” (A<B) kHz. A period Thb of the horizontal synchronizing signal b is shorter than a period Tha of the horizontal synchronizing signal a by a time ΔTh.
FIG. 18C shows a waveform of a gate signal in the case of FIG. 18A, and FIG. 18D shows a waveform of a gate signal in the case of FIG. 18B. FIG. 18E is a waveform diagram of a gate signal in the case where the gate-on voltage is made high by ΔV.
As shown in FIG. 18C, the gate pulse outputted from the gate driver has a “H (high)” level only for the same period as the period Tha of the horizontal synchronizing signal a and the gate-on voltage is held. However, although the waveform X of the gate pulse applied to the gate electrode of a TFT of a pixel close to the gate driver becomes rectangular, the rounding as shown in the drawing occurs in the waveform Y of the gate pulse applied to the gate electrode of a TFT of a pixel remote from the gate driver.
When it is assumed that a voltage (threshold voltage) at which a desired mobility can be obtained for a TFT is Va, a period of a portion of the waveform Y not lower than the voltage Va is Ta. When an area of a region surrounded by the line of the voltage Va and the waveform Y is made Sa, the dimension of the area Sa is in proportion to the quantity of electric charge written to the pixel electrode.
As shown in FIG. 18D, the gate pulse outputted from the gate driver has the “H” level for the same period as the period Thb of the horizontal synchronizing signal b, and the gate-on voltage is held. Similarly to the example of FIG. 18C, although a waveform U of a gate pulse applied to a gate electrode of a TFT of a pixel close to the gate driver becomes rectangular, the rounding as shown in the drawing occurs in a waveform W of a gate pulse applied to a gate electrode of a TFT of a pixel remote from the gate driver.
In the same manner as the above, when it is assumed that a voltage at which a desired mobility is obtained for a TFT is Va, a period of a portion of the waveform W not lower than the voltage Va is Tb. When an area of a region surrounded by the line of the voltage Va and the waveform W is made Sb, the dimension of the area Sb is in proportion to the quantity of electric charge written to the pixel electrode.
When the period Ta and the period Tb are compared, the period Tb is shorter than the period Ta by approximately ΔTh, and the area Sa>Sb is satisfied. Accordingly, in the case where the horizontal scanning frequency is relatively high as shown in FIG. 18B, insufficient writing of electric charge occurs.
In order to solve this, it is sufficient if the gate-on voltage is made high. FIG. 18E shows a gate pulse waveform in the case where the gate-on voltage is made high by ΔV in the case where the horizontal scanning frequency is “B” kHz. A waveform P of a gate pulse applied to a gate electrode of a TFT of a pixel close to the gate driver is rectangular, and the rounding as shown in the drawing occurs in a waveform Q of a gate pulse applied to a gate electrode of a TFT of a pixel remote from the gate driver.
The area of a region surrounded by the line of the voltage Va and the waveform Q becomes Sb′+ΔSb. The area ΔSb is an increment due to the rise of the gate-on voltage by ΔV. Although the area Sb is not simply equal to Sb′, it is clear that the area Sb<Sb′+ΔSb. By this, since the supply amount of electric charge is increased, the insufficient writing does not occur.
In general, a liquid crystal display device is required to be designed such that it can be sufficiently driven even by a vertical scanning frequency higher than a mainly used vertical scanning frequency so that it can support plural kinds of vertical scanning frequencies of video signals supplied from a system (for example, a personal computer) side. Accordingly, in a driving method of a recent liquid crystal display device, it is necessary to resolve the insufficient writing of gradation data due to high resolution as described above, and it is necessary to support all of plural kinds of vertical scanning frequencies supplied from the system side.
FIG. 19 shows a vertical scanning frequency, a vertical period, a horizontal scanning frequency and a horizontal period. A vertical period Tva is a period of a vertical synchronizing signal (Vsync) and is the reciprocal of a vertical scanning frequency. As shown in FIG. 19, the vertical period Tva is composed of an effective display period and a blank period. The effective display period of the vertical period Tva is a period in which the respective gate bus lines are line-sequentially driven, and FIG. 19 exemplifies gate pulse signals 1001 to 1005 outputted to the respective gate bus lines. In the blank period, the gate bus lines are not driven. On the other hand, a horizontal period Tha is the reciprocal of a horizontal scanning frequency and is almost equal to a period in which a gate pulse has an on state. When the vertical scanning frequency becomes high, the one vertical period Tva becomes short, and the horizontal period Tha in which the gate pulse is kept at the “H” level also becomes short. That is, the horizontal scanning frequency becomes high. However, there is also a case where by shortening the blank period, even if the vertical period Tva becomes short, the effective display period is not made short.
As stated above, when the vertical scanning frequency becomes high, the horizontal scanning frequency also becomes high, and a writing time of a gradation voltage to a pixel electrode becomes short. Accordingly, if the gate voltage is fixed so that writing of the gradation voltage becomes sufficient even at the upper limit of the plural kinds of vertical scanning frequencies supplied from the system side, even at a mainly used vertical scanning frequency, the gate pulse of a high gate-on voltage is outputted to the gate bus line, so that the round waveform becomes severe, and there can occur a problem in display quality.
Incidentally, the following documents are cited for reference.                [Patent document 1]        JP-A-06-230342        [Patent document 2]        JP-A-08-54859        [Patent document 3]        JP-A-11-109925        [Patent document 4]        JP-A-11-184436        